This invention relates generally to programmable logic devices and specifically to configuring a field programmable gate array (FPGA).
Referring to FIG. 1, a typical Field Programmable Gate Array (FPGA) 10 includes an array of configurable logic blocks (CLBs) 11 surrounded by input/output blocks (IOBs) 12 and embedded in a programmable interconnect structure 13 having a plurality of programmable switch matrixes (PSMs) 14. Columns containing only IOBs 12, e.g., cols. 1 and 6, are referred to as IOB columns, and columns containing CLBs 11 interposed between IOBs 12, e.g., cols. 2-5, are referred to as CLB columns. For simplicity, the FPGA 10 is shown in FIG. 1 to include 16 CLBs 12 surrounded by 20 IOBs 11 in a 6xc3x976 array, although the number of CLBs 11 and IOBs 12 may vary. In some architectures, CLBs 11 maybe defined to include adjacent portions of programmable interconnect structure 13. In actual architectures, the corner IOBs 11 may be omitted, and replaced with other circuitry such as, for instance, power and ground pads.
CLBs 11 are individually programmable to implement a variety of logic functions. IOBs 12 drive various signals between CLBs 11 and I/O pins (not shown) of FPGA 10, and programmable interconnect structure 13 (and PSMs 14) route signals between various CLBs 11 and IOBs 12. Together, CLBs 11, IOBs 12, and PSMs 14 can be programmed to implement one or more desired logic designs ranging from simple adders and multipliers to more complex structures such as microprocessors. CLBs 11, IOBs 12, and PSMs 14 of FPGA 10 are programmed by loading configuration data into an associated configuration memory array to control various switches and multiplexers therein to implement desired logic functions.
FIG. 2 shows an FPGA 20 having a configuration memory array 21 that may be used to store configuration data for the CLBs 11 and IOBs 12 shown in FIG. 1. Configuration memory array 21 includes a plurality of tiles 22a-22d that store configuration data for corresponding CLBs 11 and IOBs 12 of FIG. 1. Specifically, each tile 22a includes a plurality of columns of configuration bit cells (not shown) to store a plurality of configuration data frames for a corresponding CLB 11, each tile 22b includes a plurality of columns of configuration bit cells (not shown) to store a plurality of configuration data frames for a corresponding IOB 12 on the left and right sides of FPGA 10, i.e., cols. 1 and 6, and each tile 22c includes a plurality of columns of configuration bit cells (not shown) to store a plurality of configuration data frames for a corresponding IOB 12 on the top and bottom of FPGA 10, i.e., rows 1 and 6. The corner tiles 22d each include a plurality of columns of configuration bit cells (not shown) to store configuration data for corner IOBs 12 and/or for other FPGA elements such as ground and power circuitry. Columns including tiles 22a and 22c in array 21 are referred to as CLB tile columns, and may store configuration data for a corresponding CLB column of FIG. 1. Similarly, columns including tiles 22b and 22d are referred to as IOB columns, and may store configuration data for a corresponding IOB column of FIG. 1.
The configuration data is typically downloaded from a host system such as a personal computer or workstation and stored in an external memory 23. Upon power-up, the configuration data is read from external memory 23 to FPGA 20 as a serial bitstream. The serial bitstream is received into a configuration access port (CAP) 15, and provided in frames to a frame register 24. When frame register 24 is full, frames of configuration data are written to a column of configuration bit cells in array 21 selected by an address decoder 25 in a well-known manner. Subsequent frames of configuration data are then loaded into frame register 24 which, when full, loads the frames into another column of configuration bit cells, and so on, until array 21 is programmed.
As the size and complexity of FPGA devices increase, so does the size of the configuration bitstream which, in turn, requires larger external memory to store the configuration bitstream. As the number of configuration bits has increased from several thousand bits to several hundred thousand bits, and may soon increase beyond a million bits, the external memory is becoming undesirably large, thereby consuming more and more valuable board area. Therefore, it would be desirable to reduce the size of the external memory to conserve board area.
In accordance with the present invention, an FPGA includes a configuration control circuit having an internal memory that stores default configuration data which may configure some or all of FPGA""s logic blocks (e.g., IOBs and CLBs) into a default state. A compressed bitstream includes one or more frame control bits indicative of whether corresponding configuration data is included in the bitstream. During configuration of the FPGA, the compressed bitstream is provided to the configuration control circuit from the external memory. As each frame control bit is received, its logic state is determined. If the frame control bit indicates that corresponding configuration data is included in the bitstream, the corresponding configuration data is read from the bitstream into a frame register. If, on the other hand, the frame control bit indicates that corresponding configuration data is not in the bitstream, default configuration data is read from the internal memory into the frame register. When full, the frame register writes the configuration data to a selected column of a configuration memory array.
Each time default configuration data is retrieved from the internal memory, corresponding configuration data may be omitted from the bitstream, thereby reducing the size of the bitstream. Because the same default configuration data stored in the internal memory may be used to configure many FPGA logic blocks, the size of the internal memory is minimal. Where it is desired to configure many FPGA logic blocks into the default state, thereby writing the same default configuration data from internal memory into many configuration memory array tiles, the reduction in configuration bitstream size may be significant. The resultant compressed bitstream requires less external memory for storage, thereby allowing for a reduction in external memory size and, thus, conserving board area.